As is known, multilayered printed circuit boards (PCBs), laminate chip carriers, and the like organic products permit formation of multiple circuits in a minimum volume or space. These typically comprise a stack of electrically conductive layers of signal, ground and/or power planes separated from each other by a layer of organic dielectric material. The planes may be in electrical contact with each other by plated holes passing through the dielectric layers. The plated holes are often referred to as “vias” if internally located, “blind vias” if extending a predetermined depth within the board from an external surface, or “plated-thru-holes” (PTHs) if extending substantially through the board's full thickness. By the term “thru-hole” as used herein is meant to include all three types of such board openings.
Today's methods for fabricating such PCBs, chip carriers and the like typically comprise fabrication of separate inner-layer circuits (circuitized layers), which are formed by coating a photosensitive layer or film over a copper layer of a copper clad inner-layer base material bonded (e.g., laminated) to a dielectric layer. The organic photosensitive coating is imaged, developed and the exposed copper is etched to form conductor lines, pads and the like, depending on the desired circuit pattern. After etching, the photosensitive film is stripped from the copper leaving the circuit pattern on the surface of the inner-layer base material. This processing is also referred to as photolithographic processing in the PCB art and further description is not deemed necessary. Following the formation of individual inner-layer circuits, each including at least one conductive layer and supporting dielectric layer, a multilayer “stack” (assembly) is formed by preparing a lay-up of several inner-layers, ground planes, power planes, etc., typically separated from each other by a dielectric, organic pre-preg typically comprising a layer of glass (typically fiberglass) cloth impregnated with a partially cured material, typically a B-stage epoxy resin. Such an organic material is also referred to in the industry as “FR-4” dielectric material. The top and bottom outer layers of the stack usually comprise copper clad, glass-filled, epoxy planar substrates with the copper cladding comprising exterior surfaces of the stack. The stack is laminated to form a monolithic structure (assembly) using heat and pressure to fully cure the B-stage resin. The stacked assembly so formed typically has metal (usually copper) cladding on both of its exterior surfaces. Exterior circuit layers are formed in the copper cladding using procedures similar to the procedures used to form the inner-layer circuits. A photosensitive film is applied to the copper cladding and the coating is then exposed to patterned activating radiation and developed. An etching solution such as cupric chloride is then used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers. The resulting assembly may include as many as thirty or more conductive layers and a corresponding number of dielectric layers, all laminated into the final stacked assembly in a simultaneous manner using conventional lamination processes.
Rather than form a large assembly comprising several individual conductive-dielectric layered members, as described above, it is often desirable to initially form a stacked circuitized substrate “subassembly” including two or more conductive layers and associated dielectric layers, the laminated subassembly including a plurality of conductor pads (e.g., copper) on one or both external surfaces. These pads are often formed using photolithographic processing, as mentioned above. Two or more such subassemblies are then aligned and laminated, using an interim organic pre-preg layer such as described above, to form a final multilayered assembly. Additional individual conductor planes and dielectric layers may be included during the lamination to form even more layers for the final assembly.
In such a subassembly type of process, it is necessary to provide interconnections between the various subassemblies. This is accomplished in one manner by aligning the respective outer conductor pads on one subassembly with those on another and then bringing the two together using conventional lamination procedures. The two subassemblies are separated before lamination by an interim dielectric layer, preferably a conventional pre-preg. This dielectric serves to insulate various external conductive elements (e.g., signal lines) of one subassembly from another while allowing the designated aligned pairs of conductor pads to mate and form an electrical connection. A conductive solder paste may be used between the two mating pads to enhance the connection.
For assemblies and subassemblies as defined above, electrically conductive thru-holes (or interconnects) may also be used to electrically connect individual circuit layers and may be of one or more of the three types (buried and blind vias, and PTHs) of connections defined above. If such thru-holes are used, the bare hole walls are usually subjected to at least one pre-treatment step after which the walls of the dielectric material are catalyzed by contact with a plating catalyst and metallized, typically by contact with an electro-less or electrolytic copper plating solution. If the thru-holes are PTHs (those which extend through the entire assembly or subassembly), interconnections are thus formed between selected ones of the circuitized layers. Connectivity between aligned thru-holes of mating subassemblies is accomplished preferably using a conductive paste or the like. Such pastes are known to include a highly conductive metal such as silver in the form of flakes.
Following construction of the final multilayered assembly, chips and/or other electrical components are then mounted at appropriate locations on the exterior circuit layers of the assembly. In some examples, such components are mounted and electrically coupled using solder ball technology, one form of which is referred to in the industry as ball grid array (BGA) technology. For PCB's, these components may include capacitors, resistors, and even chip carriers. For chip carriers, a chip is often solder bonded to the carrier laminate substrate's upper surface and the carrier is in turn solder bonded to an underlying “host” substrate, typically a PCB. In either form (PCB or chip carrier), the components are in electrical contact with the circuits within the structure through the conductive thru-holes and the coupled pairs of pads (if the assembly is formed using subassemblies as mentioned), as desired. The external solder pads of the assembly designed to receive such components are typically formed by applying an organic solder mask coating over the exterior circuit layers. The solder mask may be applied by screen coating a liquid solder mask coating material over the surface of the exterior circuit layers using a screen having openings defining areas where solder mount pads are to be formed. Alternatively, a photoimageable solder mask may be coated onto the exterior surfaces and exposed and developed to yield an array of openings defining the pads. The openings are then coated with solder using processes known to the art such as wave soldering. Examples of products such as defined above are shown in the patents listed below. The listing thereof is not an admission that any are prior art to the present invention.
In U.S. Pat. No. 6,138,350, there is described a process for manufacturing circuit boards comprising providing a circuitized substrate having a dielectric surface, providing a peel apart structure including a metal layer and a peelable film, laminating the peel apart structure to the circuitized substrate with the metal layer positioned adjacent the dielectric surface, forming holes in the circuitized substrate through the peel apart structure, applying a filler material including an organic base to the peel apart structure, applying a sacrificial film onto the filler material, and applying sufficient heat and pressure to the sacrificial film to force the filler material into the holes to substantially fill the holes.
In U.S. Pat. No. 6,388,204, there is described a laminate circuit structure assembly that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.
In U.S. Pat. No. 6,440,542, there is described a copper-clad laminate which includes an insulative substrate having laminated on one or either side thereof a copper foil in which one side is roughened, the copper foil having formed on the roughened surface side thereof a metal layer whose melting point is lower than that of zinc. There is also provided a circuit board including an insulative substrate having a conductive circuit formed on one side thereof and via holes extending from the other side of the insulative substrate to the conductive circuit, there being formed between the one side of the insulative substrate and the conductive circuit a metal layer whose melting point is lower than that of zinc. No de-smearing is apparently required in making the circuit board.
In U.S. Pat. No. 6,504,111, there is described a structure for providing an interconnect between layers of a multilayer circuit board. The structure comprises a stack that includes at least one layer and a via opening that extends through at least one layer of the stack. Each individual via opening is filled with a solid conductive plug and each solid conductive plug has a first contact pad and a second contact pad.
In U.S. Pat. No. 6,593,534, there is described a method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchical wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed circuit board arrangement.
In U.S. Pat. No. 6,638,607, there is described a method of forming a member for joining to form a composite wiring board. The member includes a dielectric substrate. Adhesive tape is applied to at least one face of this substrate. At least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.
In U.S. Pat. No. 6,809,269, there is defined a circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith. One example of a product using this technology is a chip carrier. This patent is also assigned to the same Assignee as the instant invention.
In U.S. Pat. No. 6,815,837, there is defined an electronic package (e.g., a chip carrier) and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a predetermined tensile pressure. This patent is also assigned to the same Assignee as the instant invention.
In U.S. Pat. No. 6,828,514, there is defined a multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections there-between. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. This patent is assigned to the same Assignee as the instant invention.
In U.S. Pat. No. 6,955,849, there is described a method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed circuit boards and diverse electronic packages. The method involves parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed circuit boards, multi-chip modules and the like.
Complexity of the above organic products (those including organic dielectric layers, including the aforementioned PCB's and laminate chip carriers) has increased significantly over the past few years. For example, PCBs for mainframe computers may have as many as thirty-six layers of circuitry or more, with the complete assembly having a thickness of as much as about 0.250 inch (250 mils). Laminate chip carriers, in turn, may have as many as fifteen circuit layers or more as part thereof. Such organic products are known with three to five mil (a mil being one thousandth of an inch) wide signal lines and twelve mil diameter thru-holes. For increased circuit densification in many of today's products, the industry is attempting to reduce signal lines to a width of two mils or less and thru-hole diameters to two mils or less. Such high densification understandably mandates the most efficient means of interconnecting the conductor pads of the respective subassemblies when using such subassemblies to form a final multilayered circuitized substrate assembly. As defined herein, the present invention is able to accomplish this.
It is believed that a method of making a circuitized substrate assembly having organic dielectric material as part thereof which is able to assure sound, effective interconnections between various parts (subassemblies) thereof would constitute a significant advancement in the art.